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Digital Verification Engineer
Working experience with I2C, SPI, and other protocols
Good understanding of ASIC design flow
Familiarity with SystemVerilog and UVM implementation
Experience in setting up UVM test benches from scratch and developing UVM components
Experience in establishing GLS verification environments
Hands-on experience with Assertions and Functional Coverage
Automation of verification flow using Python/Perl in an industrial setting
Independent, self-motivated, team player, and able to follow through
Understanding of analog behavioral models (added advantage)
Automotive experience and requirements management experience are highly desirable
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