Role Description:
We are seeking an experienced professional to lead our verification team.
This is a permanent position based in Cork, Ireland.
* Lead and mentor the Design and Verification teams.
* Collaborate with CPU and SOC Architects to understand system requirements.
* Develop detailed test and coverage plans based on architecture and micro-architecture.
* Create and maintain verification environments, including stimulus, checkers, assertions, and coverage.
* Execute verification plans, including design and environment bring-up, regression testing, and debugging.
* Track and report progress using metrics like bugs and coverage.
Key Responsibilities:
The ideal candidate will have expertise in microprocessor verification, including cache coherence, memory ordering, branch prediction, and address translation.
Experience with Random Instruction Sequencing (RIS) and testing at block/unit and subsystem/chip levels is essential.
A proven ability to lead a small team of verification engineers is necessary.
Knowledge of advanced techniques like formal verification, assertions, and silicon bring-up is also required.
Proficiency in writing test plans, portable testbenches, and assembly code is necessary.
Familiarity with verification tools and methodologies, including simulators, gate-level simulation, and formal proof tools, is desirable.
Benefits and Requirements:
This role offers a unique opportunity for professionals to develop their skills and expertise in verification engineering.
* Expertise in microprocessor verification, including cache coherence, memory ordering, branch prediction, and address translation.
* Experience with Random Instruction Sequencing (RIS) and testing at block/unit and subsystem/chip levels.
* Proven ability to lead a small team of verification engineers.
* Knowledge of advanced techniques like formal verification, assertions, and silicon bring-up.
* Proficiency in writing test plans, portable testbenches, and assembly code.
* Familiarity with verification tools and methodologies, including simulators, gate-level simulation, and formal proof tools.