Company:
QT Technologies Ireland Limited
Job Area:
Engineering Group, Engineering Group > ASICS Engineering
General Summary:
As a member of the Graphics team, you will help develop new flows, methodologies, and algorithms to improve power, performance, and area (PPA) on state-of-the-art GPU cores while working closely with the graphics microarchitecture design and implementation teams.
You will possess a basic understanding of RTL design and the ASIC design flow from RTL to GDS, including synthesis, static timing analysis, formal verification, physical design, ECO generation, and verification.
You will collaborate with multiple functional teams—including design, technology, power, implementation, sign-off, and post-silicon—to drive PPA improvements into GPU cores.
Knowledge and Experience:
Implementation and delivery of GPU cores from RTL to GDSII
Semi-custom design flow and methodology development
Identifying areas for flow and process improvements
Verilog and System-Verilog languages
RTL synthesis using physically aware tools
Design constraint management for power, timing, clocking, interfaces
Formal verification for RTL-netlist and netlist-netlist checks
Clock tree analysis and optimization
ECO methods for functional and timing fixesManaging design goals and tradeoffs in power, performance, and area
Preferred Qualifications:
At least 5–7 years of experience developing methodologies for PPA improvement
Basic understanding of digital design and RTL development
Hands-on experience with EDA tools such as Synopsys Fusion Compiler, Synopsys RTL-Architect, PrimePower, PrimeTime, and Prime Closure
Script writing experience in Unix shell, Python, Perl, and/or TCL
Excellent interpersonal and analytical skills and ability to work independently
Highly motivated, excellent team spirit, obsession with deliverable quality and customer orientation
Preferred education: Master's in Computer Engineering, Computer Science, or Electrical Engineering
Required education: Bachelor's in Computer Engineering, Computer Science, or Electrical Engineering
Minimum Qualifications:
Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience
Benefits:
Salary, stock, and performance-related bonus
Maternity/Paternity leave
Employee stock purchase scheme
Matching pension scheme
Education assistance
Relocation and immigration support (if needed)
Life, medical, income, and travel insurance
Subsidised memberships for physical and mental well-being
Bicycle purchase scheme
Employee run clubs (running, football, chess, badminton, and many more)
Equal Opportunity
We are an Equal Opportunity employer; all qualified applicants will receive consideration for employment without regard to race, colour, religion, sexual orientation, gender identity, national origin, disability, veteran status, or any other protected classification.
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