Senior Digital Design Engineer
Develop and implement cutting-edge digital design solutions for ASIC or FPGA platforms. Lead the development of high-quality RTL using Verilog or VHDL, with a focus on synthesis, timing closure, and integration activities.
Key Responsibilities:
* Drive architecture definition and specification development for digital IP
* Collaborate with verification teams to achieve functional coverage and UVM-based testbench implementation
* Guide and review synthesis, timing closure, and integration processes
* Design and deliver high-performance digital systems
Requirements:
* Minimum 7 years of experience in digital design within a semiconductor or related industry
* Proven expertise in RTL design (Verilog/VHDL), with a strong understanding of SoC architecture
* Proficiency in industry-standard EDA tools for synthesis, timing, and simulation
This role requires a highly skilled digital design engineer with a strong background in ASIC/FPGA platform design,RTL design, and EDA tool expertise.
Relevant skills and qualifications include:
* Strong technical knowledge of digital design principles and methodologies
* Experience with industry-standard EDA tools and software
* Excellent communication and collaboration skills
* Ability to work effectively in a team environment