Staff CPU Physical Design Engineer – High-Performance ASICs
We are currently partnered with an industry leading semiconductor company in Ireland looking to expand their headcount at their central European R&D Centre with a Staff CPU Physical Design Engineer.
This role is ideal for an experienced engineer looking to lead complex physical design efforts across the full ASIC development lifecycle—from architectural definition through tape-out.
This is a permanent working opportunity based in Cork, Ireland.
Key responsibilities for this Staff Physical Design Engineer position:
Lead physical design of digital and/or analog IP to meet aggressive power, performance, and area (PPA) goals
Define architectures, circuit-level specifications, and simulation strategies
Own end-to-end ASIC development: RTL, synthesis, P&R, STA, and sign-off
Work cross-functionally with system architects, hardware, and software teams to ensure implementation success
Utilize industry-standard tools for RTL-to-GDS flows and physical implementation (e.g., Virtuoso, Synopsys, Cadence)
Prepare technical documentation and mentor junior engineers
Key requirements:
Bachelor's degree with 6+ years, Master's with 5+ years, or PhD with 4+ years of experience in ASIC/SoC design and physical implementation
Proficient in architecture-level planning, RTL design, verification, and physical closure
Strong background in digital/analog IP development and IC package integration
Skilled in scripting (Tcl, Python, Perl) and use of design/verification tools
Proven ability to lead projects and collaborate with senior technical and leadership teams
Keywords:
ASIC / Physical Design / SoC / RTL / CPU Design / Low-Power Design / Synthesis / Place & Route / STA / RTL-to-GDS / IP Design / High-Performance Computing / IC Packaging / Digital Design / Cadence / Synopsys / Virtuoso / Semiconductor / Timing Closure / PPA Optimization
If you are interested in this Staff CPU Physical Design Engineer position, please send a CV to
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