Overview
We are looking for a Senior Staff Engineer to join a world leading semiconductor powerhouse at their site in Cork. You will drive the development and deployment of FPGA-based emulation systems. You will be responsible for creating robust pre-silicon environments that bridge the gap between hardware design and software enablement, ensuring the successful launch of complex SoC projects.
As a Senior Staff Engineer, your responsibilities will include:
Responsibilities
Emulation Strategy: Provide end-to-end hardware emulation services utilizing industry-standard platforms such as Palladium, Veloce, and specialized FPGA prototyping systems.
Technical Workflow Management: Oversee the entire implementation pipeline, including RTL synthesis, physical mapping (place & route), defining timing constraints, and managing complex clocking architectures to achieve closure.
System Bring-Up & Debugging: Spearhead the diagnostic process for SoC initialization by analyzing waveforms and employing advanced instrumentation to resolve system-level bottlenecks.
Hardware Evolution: Direct or assist in the introduction of next-generation prototyping hardware and the software tools required to run them.
Multidisciplinary Collaboration: Partner with international teams across CAD, software development, design, and verification to align technical goals.
Vendor & Industry Engagement: Act as a primary liaison with EDA tool providers and represent the organization’s technical interests in executive-level forums.
Leadership & Mentorship: Provide technical direction and professional coaching to early-career engineers within the department.
Qualifications
Bachelor's, master’s or PhD in a quantitative engineering field like Electronics, Computer Engineering, or Computer Science
5+ years’ in verification, design, or emulation of FPGA systems
Proficiency in SystemVerilog or similar HDL for complex logic design
Extensive practical experience with high-end FPGA architectures (e.g., Xilinx UltraScale/UltraScale+ or MPSoC series); familiarity with Altera/Intel platforms is a plus
Proven track record of standardizing emulation methodologies and build-scripts at an enterprise scale
Deep insight into CPU/SoC structures (including NoC and power management) and experience with low-level debugging tools like JTAG or kernel-level probes
Proficiency in C/C++ for hardware-software interaction and scripting languages (Python/TCL) for workflow automation
Thorough grasp of the procedures required for timing closure and standard FPGA development flows
Ability to work autonomously while maintaining strong communicative ties with a global team
Feel free to also refer someone you may know who could be good for the role. If they are successfully placed, we offer a great referral scheme!
Key words – FPGA Design / FPGA Prototyping / FPGA Emulation / FPGA Architectures / Pre-silicon / JTAG / Debugger / TCL / Python / SoC / CPU /
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