Social network you want to login/join with:Senior Digital Design EngineerWe’re looking for a Senior ASIC Digital Design Engineer.Experience requiredRTL Design with SystemVerilogLinting checks with SpyGlassStatic Timing Analysis (STA)SynthesisExperience with formal verification would be a plusKey QualificationsBS/MS degree with a minimum of 8 years of related experienceProficient in scripting languages (Python, Tcl, Perl, Unix shell)Familiar with RTL best design practices with SystemVerilogFamiliar with implementation and verification front-end flowsStrong communication skills
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