The team that built the innovative Silicon IP AZ1 Neural Edge, powering the latest generation of Echo devices, is seeking a Senior ASIC Design Engineer to continue driving innovation for our customers. We are part of Amazon Lab126, known for revolutionizing reading with Kindle and reimagining user experience through Echo and Alexa. Join us to build on the success of our first-generation ML accelerator at the edge.
Work hard. Have fun. Make history.
Key job responsibilities
In this role, you will work within a team developing SoCs for Amazon devices. Responsibilities include designing RTL components, integrating third-party and internal IPs into Amazon SoCs. You should have in-depth knowledge in areas such as fabric, memory controllers, CPU, caches, coherence, MMU, security, and high-speed interfaces/protocols for integrating IPs and common SoC blocks. Collaboration with system architects, IP developers, and physical design teams is essential to meet power, performance, and area goals. You will also help define processes, methods, and tools for designing and implementing complex large-scale SoCs.
* Work with Chip Architects to understand architecture and product requirements.
* Translate chip specifications into RTL using internal and external IPs.
* Review architecture and design of custom IPs for SOC integration.
* Develop methodologies for I/O, DFT, debug, clocking, and power management.
* Design and develop RTL for interfaces, power management, clocking, testing, and debugging.
* Provide technical leadership through mentorship and teamwork.
BASIC QUALIFICATIONS
* BS degree or higher in EE, CE, or CS with 10+ years of practical semiconductor design experience, including full-chip and subsystem integration.
* Experience in micro-architecture definition based on architecture guidelines and model analysis.
* Strong experience with PCIe.
* Proficiency in RTL coding (Verilog/SystemVerilog), debugging, and performance/power/area trade-offs.
* Experience in full-chip and subsystem timing closure with synthesis and static timing analysis teams.
* Successful tapeouts of complex, high-volume SoCs in advanced nodes.
* Experience with DFT tools for scan and BIST insertion.
* Excellent communication, collaboration, and teamwork skills, with the ability to contribute to diverse teams.
PREFERRED QUALIFICATIONS
* Deep knowledge in areas like CPU, DSP, or programmable accelerators.
* Design experience in datapath, flow control, arbitration, FIFO, DMA, IOMMU, SOC bus architectures, Arteris NOC, ARM’s AXI/AHB protocols, serial interfaces (PCIe, I2C, UART, USB, etc.), LPDDR controllers, embedded memories, and IP integration.
* Experience with RTL power analysis, gate-level testing, multi-clock design practices, and ASIC post-silicon validation.
* Experience working with software teams on HW/SW interfaces, control and status registers, and error handling.
* Close collaboration with physical design teams for optimized ASICs focusing on power, performance, and area.
We are committed to an inclusive culture that empowers Amazon employees. If you need accommodations during the application or onboarding process, please visit this link. Amazon is an equal opportunity employer and does not discriminate based on veteran status, disability, or other protected classes.
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