Client:
Our client a leading Multinational Semiconductor PMIC Company requires Senior Staff Verification Engineer for role based either in Limerick or Cork, Ireland. The role requires the candidate to be onsite a minimum of 3 days per week.
Role:
You will contribute to the success of the company by working together with design, firmware and hardware emulation teams to ensure that proprietary power devices are verified for performance, completeness and correctness.
Responsibilities:
1. Architecture of Verification Environments for block, subsystem, and SoC level designs.
2. Development of UVM-SV Scoreboards for self-checking regressions.
3. Development of Functional Coverage items like Covergroups and Corverpoints as part of Metric Driven Verification Environments.
4. Development of SystemVerilog Assertions for use in Simulation Environments.
5. Definition and Management of Verification Plans (vPlans) using Cadence vManager tools.
6. Creation and Management of Automated Regression Environments.
7. Verification scope will encompass analog, digital, and firmware functions as well as evaluation and benchmarking of full system performance.
8. Work closely with analog designers, digital designers, systems architecture, firmware, applications, and test engineering to specify, design, develop, and manage a verification system for SOC.
9. Knowledge of protocol interfaces for spec compliance (PMBus, SVI, SVID, I2C, AHB etc.).
10. Track and report progress of the projects against key milestones.
11. Provide an environment where collaboration, effective communication, and learning are fun and rewarding.
12. You will have a comprehensive, demonstrable background in power semiconductors / semiconductor physics and/or electronics engineering.
13. You will approach tasks in a logic-based way, along with having the ability and motivation to develop novel and creative ideas.
14. Your communication skills will enable seamless collaboration both with our manufacturing partners and internally, and you will know how to build and maintain lasting relationships in international and cross-functional project teams.
Education:
1. PhD, post-graduate or degree qualification in Electronic Engineering or similar.
Experience:
1. 10+ years’ relevant engineering experience.
2. Experience of full-product verification flows, including HW & FW.
3. Experienced with constrained-random verification environment and flow build-up with UVM, Coverage-Driven verification methodology.
4. Experienced with Assertions like System Verilog Assertions.
5. Experience with vManager, vPlan and Regressions, etc.
6. Experience working on mixed-signal ICs is a plus.
7. Experience with debugging test failures and report verification result to achieve the expected functional/code coverage goals.
8. Extensive usage of RTL simulation tools.
9. UVM, System Verilog, Perl/Python shell-scripting skills required.
10. Excellent interpersonal and communications skills.
11. The ability to work with cross-functional teams and support and mentor less experienced team members.
Contact:
For further information please contact Mícheál at Software Placements on 00353 1 5254642 or email micheal@softwareplacements.ie
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