Our organization is at the forefront of Multinational Semiconductor EDA Software development, driving innovation in Wireline technology at unprecedented data rates (112Gbps+). We are seeking talented analog designers to work on cutting-edge products for high-speed communication protocols such as PCIe and UCIe. Key responsibilities include designing High Speed SERDES products exceeding 112 Gbps on leading edge technology nodes (e.g. 3nm FinFET CMOS), developing analog/mixed signal IC circuit blocks, and collaborating closely with Physical Design Engineers.
We are looking for technical leaders who can participate in circuit design and SERDES architectures, possessing strong communication skills and the ability to work cooperatively in a team environment. Required qualifications: Minimum 3-5 years experience in CMOS SERDES or high-speed I/O IC design and development, thorough understanding of jitter and signal equalization techniques, proficient design experience in many SERDES circuit blocks, excellent problem-solving skills, and analog aptitude.
Benefits of working with us include opportunities for professional growth and development, collaboration with experienced engineers, and participation in state-of-the-art projects. Education: BEng, MEng, or PhD. Advantageous skills: Cadence tool experience and design experience at >10Gbps and in <40nm technologies.
Requirements: Minimum 3-5 years experience in CMOS SERDES or high-speed I/O IC design and development, thorough understanding of jitter and signal equalization techniques, proficient design experience in many SERDES circuit blocks, excellent problem-solving skills, analog aptitude, good communication skills, and education: BEng, MEng, or PhD.