Senior Engineer – STA / P&R / Physical Design
We are seeking a Senior Engineer to join a leading semiconductor company at their Cork site.
This role involves optimizing timing methodologies for high-performance, low-power semiconductor designs, including refining characterization techniques, improving timing models, and enhancing sign-off processes in collaboration with engineering teams.
Responsibilities:
Develop and refine timing analysis methodologies, including library characterization and advanced modeling techniques such as SOCV/POCV, AOCV, LV, etc.
Ensure timing accuracy through correlation of results between SPICE simulations and sign-off tools.
Automate workflows using scripting languages like Python, Perl, TCL, and Bash.
Optimize standard cell libraries for timing and reliability in advanced process nodes.
Apply static timing analysis (STA) techniques and collaborate with physical design teams to improve timing closure strategies.
Contribute to research and implementation of next-generation timing solutions for cutting-edge technologies.
Skills and Experience:
5+ years’ experience in timing analysis, modeling, and methodology development.
Strong knowledge of timing constraints, sign-off processes, and automation scripting.
Familiarity with advanced semiconductor process technologies and reliability modeling.
Excellent problem-solving skills and ability to work collaboratively in a multidisciplinary team.
Feel free to refer someone suitable for this role. Successful referrals are rewarded through a referral scheme.
Additional Information:
Seniority level: Mid-Senior level
Employment type: Full-time
Job functions: Engineering, Manufacturing, and Other
Industries: Engineering Services, Semiconductor Manufacturing, Computers and Electronics Manufacturing
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