Lead Verification Expert for ASIC Development
We are seeking a skilled and experienced Lead Verification Engineer to join our team. As a key team lead and principal consultant, you will be responsible for developing verification environments from scratch using UVM.
The successful candidate will have a strong understanding of UVM and ASIC design verification, as well as good knowledge of scripting languages such as Python, CSH, and Make.
This role is ideal for an experienced engineer looking to take on a leadership position and drive the development of cutting-edge ASICs, SoCs, and IPs.
Key Responsibilities:
* Develop verification environments from scratch using UVM.
* Create test cases for ASICs / IC'S / SoCs.
* Provide regression debug support and infrastructure development.
Requirements:
* Strong understanding of UVM and ASIC design verification.
* Good knowledge of scripting language such as Python, CSH, Make.
* SystemC / C/C++ is a plus.
This is a unique opportunity for an experienced engineer to take their career to the next level and contribute to the development of innovative technology solutions.