Security HW Design Verification Engineer – SoC Security / UVM / Cryptographic IP
We are currently partnered with a leading semiconductor organisation developing advanced security IP and secure processing technologies for next-generation mobile, compute, and data centre platforms. As part of their expanding security engineering group, they are looking to hire a Security HW Design Verification Engineer to contribute to the verification of highly secure SoC subsystems and hardware root-of-trust architectures.
Key responsibilities
Develop and execute verification strategies for advanced security-focused SoC subsystems and IP blocks
Design and maintain unit-level and SoC-level verification environments using industry-standard methodologies such as UVM, OVM, or VMM
Contribute to the verification of complex secure subsystems including CPUs, NoCs, cryptographic accelerators, key management, and secure processing engines
Support Gate-Level Simulation (GLS) verification flows for secure SoC validation
Key requirements
Bachelor’s degree in Engineering, Computer Science, Electronics, or related technical discipline
Experience in hardware design verification for SoC or subsystem-level environments
Strong understanding of SoC verification methodologies and industry-standard verification flows
Hands‑on experience developing verification environments using UVM, OVM, or VMM methodologies
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