Our organization seeks a seasoned verification expert to fill this critical role. As a Senior Verification Engineer, you will collaborate with diverse teams to verify the performance, completeness, and accuracy of power devices at various levels.
Key Responsibilities:
* Develop verification environments for complex digital and mixed-signal designs.
* Create UVM-SV scoreboards, functional coverage items, and SystemVerilog assertions for simulation.
* Manage verification plans using advanced tools.
* Design and maintain automated regression environments.
* Collaborate closely with analog, digital, and firmware teams to specify, design, and manage verification systems.
* Ensure compliance with interface protocols such as PMBus, I2C, AHB, etc.
Requirements:
* Bachelor's or Master's degree in Electronic Engineering or related field (PhD preferred).
* At least 10 years of experience in verification, with expertise in both hardware and firmware.
* Proficiency in UVM, SystemVerilog, and assertions.
* Experience with advanced verification management tools.
* Strong background in RTL simulation tools and debugging test failures.
This is an exciting opportunity to contribute to cutting-edge technology in a collaborative environment.