Senior Design Verification Engineer - Power Aware / UVMWe are supporting a semiconductor innovator and they are hiring a Senior Design Verification Engineer focused on power aware verification for advanced video and vision hardware.
Please note, this will be predominantly onsite, with little to no flex on hybrid working About them: The team delivers complex IP used in high performance consumer and automotive platforms.
You will join a group that owns verification quality from early testbench architecture through post silicon debug.
The environment is highly technical, collaborative, and built around modern verification flows.
You will architect System Verilog and UVM testbenches, build power aware verification using UPF, and drive both functional and low power simulations.
You will partner closely with RTL, DFT, firmware, and physical design teams.
What you will do: Develop UVM environments for complex multimedia and CV IPCreate UPF based power aware verification flows Run functional, gate level, and power aware simulations Write and maintain reusable UVM sequences Debug issues across simulation and silicon Automate regressions with Python or Perl Contribute to performance, area, and power quality goals Support and mentor junior engineers What they look for: Strong System Verilog and UVM expertise Hands on UPF experience History of successful tapeouts and post silicon debug Proficiency with Python or C++ for test content and analysis Background in computer vision or video hardware is an advantage Ability to collaborate across large cross functional teams What is in it for you?High visibility in a team that owns verification for flagship IPTechnical leadership opportunities A chance to influence design quality at scale Play a key role in a fast paced engineering environment Receive an excellent total package consisting of base, bonus, RSU, bonus RSU and relocation assistance if needed.
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