Backend Design Engineer
Cadence seeks skilled engineers to develop and implement cutting-edge design solutions. This role offers the opportunity to work on complex digital projects, pushing the boundaries of technology.
The ideal candidate will possess a deep understanding of digital microarchitecture definition and documentation, as well as RTL logic design, debug, and functional verification.
* Key Responsibilities:
* Understanding of Digital microarchitecture definition and documentation
* Understanding of RTL logic design, debug and functional verification
* Understanding of IP integration and verification
* Understanding of digital architecture trade-offs for power, performance, and area
* Understanding of proper handling of multiple asynchronous clock domains and their crossings
* Understanding of synthesis timing constraints, static timing analysis and constraint development
* Understanding of fundamental physical design flows, e.g. floor planning and clock tree synthesis
* Understanding of the impacts of Analog and mixed-signal design and verification on digital-on-top development flow.
* Experience with FPGA and/or emulation platform
* Firmware development of embedded microcontroller systems is a plus.
Requirements:
* Minimum 5 years of ASIC backend design experience.
* Must have gone through successful tapeouts in advance technology nodes
* Substantial experience with Verilog is required, as are excellent logic and debug skills.