A leading semiconductor IP organisation is looking to hire a Principal Verification Engineer to support the development of high-performance memory controller IP used across data-intensive and next-generation compute applications.As a Principal Verification Engineer you will:Define and architect scalable UVM-based verification environments for complex controller IPDevelop self-checking testbenches, scoreboards, and coverage models to support metric-driven verificationCreate and deploy assertions for both simulation and formal verification flowsOwn and maintain verification plans, ensuring alignment between specification and coverage targetsDrive regression strategy and automation in collaboration with CAD/flow teamsWork closely with RTL designers to debug and resolve challenging corner-case scenariosContribute to technical reviews and quality processes across the development lifecycleThis role requires someone comfortable operating at a senior technical level, influencing methodology decisions and mentoring others within the verification team.What they’re looking forStrong background in SystemVerilog and UVM in a production environmentExtensive experience verifying complex digital IP or SoC subsystemsSolid understanding of RTL design principles and debug methodologiesProven experience with coverage-driven verification strategiesExposure to AMBA-based protocols (e.g., AXI or CHI) would be beneficialTel - 01189073075LinkedIn - https://www.linkedin.com/in/jordan-browne-b4a08b20b/
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