We are currently partnered with a leading semiconductor organisation developing advanced high-performance, low-power SoCs and compute cores. As part of their timing and signoff engineering group, they are looking to hire an STA Design Engineer to drive static timing analysis, timing closure, and methodology development across complex ASIC and SoC programs.
Key responsibilities
Perform static timing analysis and timing closure for complex ASIC cores and full-chip SoCs
Develop and refine STA methodologies, signoff flows, and timing closure techniques
Conduct timing analysis on gate-level place-and-route netlists to ensure timing and power targets are achieved
Collaborate closely with RTL, synthesis, and physical design teams to improve power, performance, and area (PPA)
Key requirements
4+ years of experience in static timing analysis, timing closure, or ASIC signoff engineering
Strong expertise with STA tools such as PrimeTime, PrimeShield, or Tempus
Hands‑on experience with ECO and timing closure tools such as Tweaker, PrimeClosure, PTECO, or Tempus ECO
Strong understanding of ASIC design flows from RTL‑to‑GDS
Keywords
STA / Static Timing Analysis / Timing Closure / ASIC / SoC / PrimeTime / Tempus / PrimeShield / ECO / PPA Optimization / RTL-to-GDS / Timing Signoff / Physical Design / Synthesis / Python / Tcl / Perl / Semiconductor / Low Power Design / Signoff Engineering
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