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Job Description:
The Networking and Connectivity Solutions (NCS) BU of Microchip is building a highly skilled R&D group in Cork focusing on Analog, Digital and Communication system design areas. NCS has a broad portfolio of networking products including Ethernet, Single-Pari Ethernet, PCIe, USB and PoE.
NCS develops networking ICs and software for a broad range of applications ranging from 10 Mbps to 12.5 Gbps speed grades targeting automotive and industrial markets. NCS has been a leader in several new technologies over the last 20 years and has been providing long lasting products in the rigorous automotive market.
NCS has a global presence with teams in multiple locations. The NCS team in Cork is seeking Senior Ethernet PHY designers to join our world-class team and drive the development of cutting-edge multi-gig T1 PHY products.
The role will include working in the areas of RTL design, design verification, synthesis, STA, and Test using an industry leading ASIC design flow. Candidate will also be responsible for training and mentoring junior engineers to grow the team's capability. This position requires a proactive and motivated candidate with a proven record of success in a cross functional and cross site team environment.
What's attractive about this opportunity:
This position will expose you to the challenging world of embedded controller design in automotive information and serial communication systems. You will play a key role in the architecture, design, and verification of high-performance multi-gigabit T1 Ethernet PHYs.
Key job responsibilities/duties include:
* Lead the design and development of DSP algorithms and architectures.
* Translate high-level DSP algorithms into efficient RTL code for ASIC implementation.
* Perform functional verification and bit-matching with the system-model.
* Analyze and optimize power, area, and performance trade-offs in the DSP designs.
* Pre-Silicon FPGA design emulation.
* Collaborate with system architects, analog/mixed-signal designers, and verification teams.
* Drive design reviews, documentation and provide technical mentorship to junior engineers.
Requirements/Qualifications:
* Bachelor's degree in science, engineering, or related field.
* 10+ years of experience in digital ASIC design.
* Strong experience in digital design, RTL coding, and ASIC/FPGA development flows.
* Understanding of DSP theory and implementation for high-speed serial communications.
* Working with global team experience.
* Familiar with function verification with Verilog/System-Verilog.
* Excellent analytical, problem-solving, and communication skills.
* Experience with automotive and industrial Ethernet standards (e.g., 802.3bp, 802.3ch, 802.3cg) is highly desirable.
* Experience in MATLAB is a plus.
Travel Time:
0% - 25%
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