Job DetailsThe CEG NAG (Networking Architecture Group) is Intel's premier team focused on defining the future of high-performance networking silicon. The team architects next-generation networking solutions that enable hyperscale data centers, cloud infrastructure, and AI workloads to achieve unprecedented performance and efficiency. Specializing in IPU/DPU platforms, advanced packet processing architectures, and programmable networking technologies, the group forms the backbone of modern distributed computing systems.About the RoleWe are seeking a Senior SoC Compute & Memory Architect to define and drive the architecture of compute complexes and high‑performance memory subsystems for next‑generation IPU/DPU platforms. The role is responsible for end‑to‑end architecture of CPU clusters, cache hierarchies, coherency models, and memory subsystems. You will optimize system‑level performance, scalability, power efficiency, and programmability while ensuring seamless interaction with networking, storage, and accelerator subsystems in hyperscale environments.Key ResponsibilitiesCache Hierarchy and Coherency ArchitectureDefine and evolve multi‑level cache hierarchy (private/shared caches, system‑level cache).Architect coherency models across compute cores, accelerators, and IO subsystems (coherent vs non‑coherent interactions).Evaluate trade‑offs between latency, bandwidth, scalability, and coherence domain complexity.Memory Subsystem ArchitectureArchitect system memory subsystems including DDR/LPDDR interfaces, memory controllers, and scheduling policies.Work with the performance architect to define memory access models for compute, network, and accelerator subsystems.Ensure optimal balance between latency‑sensitive control workloads and bandwidth‑intensive datapath workloads.IO Memory and Virtualization Architecture (SMMU/IOMMU)Define architecture for SMMU/IOMMU supporting virtualization‑heavy IPU workloads.Architect features such as multi‑tenant isolation, security boundaries, and shared vs isolated memory models.Ensure efficient interaction between host, IPU/DPU compute, and offload engines.System‑Level Integration (Compute, Network, Storage)Architect integration between compute subsystem, network subsystem (packet processing pipelines), and storage/accelerator subsystems.Optimize data movement across subsystems to minimize copies, latency, and bandwidth overhead.Drive system architecture decisions for balanced SoC performance.Power, Efficiency, and Scaling StrategyDefine compute and memory strategies for power efficiency and DVFS scalability.Architect mechanisms for memory bandwidth throttling/prioritization and per‑subsystem scaling.Optimize performance‑per‑watt at the system level.Multi‑Generation Architecture RoadmapLead long‑term roadmap for compute and memory evolution across IPU/DPU product generations.Define scaling strategies for core count and frequency, memory bandwidth and capacity, cache scaling and topology.Ensure backward compatibility and smooth migration across product lines.Cross‑Functional LeadershipCollaborate with teams across networking subsystem (NSS), SoC fabric/interconnect, firmware, OS, drivers, and validation/performance modeling.Drive architecture alignment and resolve cross‑domain trade‑offs.Behavioral TraitsArchitectural vision – defines long‑term strategy across system domains.Influence without authority – drives alignment across multiple teams and disciplines.Systems thinking – understands interactions across compute, memory, network, and software.Decision‑making under ambiguity – makes sound trade‑offs with incomplete data.Collaboration – builds strong cross‑functional relationships.Customer‑oriented mindset – translates workload needs into architectural innovations.Ownership and accountability – drives initiatives end‑to‑end.Continuous learning – stays current with evolving compute and memory technologies.QualificationsMinimum QualificationsBachelor's degree in Electrical Engineering, Computer Engineering, or a STEM related field.10+ years of experience in SoC/CPU/memory subsystem architecture.Experience with CPU architecture and cache hierarchies.Experience with memory subsystems (DDR/HBM, controllers, QoS).Experience with coherent/non‑coherent interconnect architectures.Experience in system‑level performance and PPA trade‑off analysis.Experience driving architecture definition from concept to silicon.Preferred QualificationsPost‑graduate degree in Electrical Engineering, Computer Engineering, or a STEM related field.Experience with ARM and x86 compute and memory subsystems, including NUMA systems, cache coherency, or large‑scale platform architectures.Experience with IPU/SmartNIC or accelerator‑centric SoCs, particularly in cloud and hyperscale environments.Familiarity with PCIe, CXL, and memory semantics for high‑performance IO.Track record of multi‑generation architectural ownership and mentoring other architects.SalaryAnnual Salary Range (Ireland): €75,200.00 – €139,700.00. Compensation is based on job‑related skills, experience, and education. The final offer may include additional pay components and benefits.Work ModelHybrid work model: employees can split time between on‑site at the assigned Intel site and off‑site.EEO StatementAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.BenefitsIntel invests in our people and offers a complete and competitive package of benefits for employees and their families through every stage of life.
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