Responsibilities
Deploying industry-leading verification methodologies such as UVM and formal verification
Developing testbenches and verification components such as UVCs, C models, and vertical/horizontal reusable verification environments
Verifying sensor algorithm RTL for ASIC tapeout quality delivery
Test plan development based on design documents and interaction with design/systems engineers
Implementing C model integration within UVM framework
Writing SystemVerilog assertions
Debugging, verifying, optimizing, and bit‑exact matching with test vectors
Analyzing coverage data and working with design teams to address coverage holes
Develop/augment framework for running regressions
Debugging regression failures with design/systems teams
Support integration of design in higher‑level subsystem including test planning, test vector delivery, and debug of test vectors at the integration level
Python automation for improving workflows and team efficiency
Participate in all project reviews
Support software and other teams with debug
Documentation
Qualifications
Bachelor's degree in science, engineering, or related field
6+ years ASIC design verification, UVM‑based functional verification, or related work experience
Experience using formal verification tools like Jasper or VC_Formal is a plus
Experience with SystemC and Matlab is a plus
Gate‑level simulation debug and usage of power extraction tools is a plus
Experienced with constrained‑random verification environment and flow build‑up with UVM, coverage‑driven verification methodology
Experienced with assertions, such as SystemVerilog Assertions
Experience with debugging test failures and reporting verification results to achieve expected code/functional/line coverage goals
Extensive usage of RTL simulation tools
UVM, SystemVerilog, Perl/Python shell‑scripting skills required
Familiarity with C/C++
Strong analytical skills and ability to work in a dynamic and fast‑paced team environment
Excellent written and verbal skills
Strong interpersonal skills and a good team player
Location
Cork has a proud reputation as Ireland's second largest economic engine and is now one of the Top 20 location choices in Europe with 39,000 people being employed by over 170 overseas companies. There's a growing diversity in the region with people from many nationalities relocating to Cork, relishing the opportunity to work and live in a location that offers an excellent quality of life. A gateway to Europe, Cork airport provides access to almost 50 international destinations including transatlantic air routes.
Equal Opportunities
We are an Equal Opportunity employer; all qualified applicants will receive consideration for employment without regard to race, colour, religion, sexual orientation, gender identity, national origin, disability, veteran status, or any protected classification.
Benefits
Salary, stock and performance‑related bonus
Maternity/Paternity Leave
Employee stock purchase scheme
Matching pension scheme
Education Assistance
Relocation and immigration support (if needed)
Life, medical, income and travel insurance
Subsidised memberships for physical and mental well‑being
Bicycle purchase scheme
Employee run clubs, including running, football, chess, badminton and many more
Minimum Qualifications
Bachelor's degree in science, engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience
Master's degree in science, engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience
PhD in science, engineering, or related field
References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.
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