ASIC Verification Engineer Job Description
The ASIC Verification Engineer is responsible for developing System Verilog – UVM testbenches and solving complex problems related to test bench development. This role requires a strong background in Digital Logic Design and Verification, as well as experience working with CAD/EDA tools for Design and Simulation.
Main Responsibilities
* Develop System Verilog – UVM testbenches
* Solve complex problems related to test bench development
* Develop UVC components for new verification environments from scratch;
* Define and write functional coverage models;
* Debug failing test cases to root cause;
* Participate in reviews to ensure test bench meets quality and is complete;
* Contribute to verification perspective in Design and Concept meetings;
* Ensure test bench meets sign-off targets, including coverage, functional safety and test bench qualification;
* Proactively help increase efficiency of verification activities and mitigate risks early;
* Contribute to enhancing Verification strategy and architecture of IP testbenches.
Requirements
* At least 8 years of experience in Verification working with Verilog and/or SystemVerilog;
* 5 years of experience on IP/block level Test-bench bring up on SV UVM based platform;
* The ability to understand complex design specification, derive features and test bench architectures from concept;
* Familiarity with CAD/EDA tools for Design and Simulation;
* Working knowledge in scripting languages for verification environments (Python, Perl, TCL would be preferred);
* Strong background in Digital Logic Design and Verification