Job Title: Principal Analog Layout Engineer
Client: Chipright
Location: Galway, Ireland
Job Category: Other
EU Work Permit Required: Yes
Job Description
This role involves leading the design and development of high-performance analog circuits for digital systems. The ideal candidate will have extensive experience in layout design and a deep understanding of timing critical circuits.
* We are seeking an experienced Principal Analog Layout Engineer to lead our team in the development of cutting-edge analog designs.
* The successful candidate will have a strong background in layout design, with a focus on 65nm and below technologies.
* A key aspect of this role is ensuring that all designed layouts meet strict timing requirements, particularly for PLLs, DLLs, and clock distribution networks.
* Mastery of matching techniques for timing circuits and current cells is essential for success in this position.
* Bonus points will be awarded for experience with chip finishing processes.
* Familiarity with Cadence PVS/QRC/Pegasus tools is required.
Key Responsibilities:
* Lead the design and development of high-performance analog circuits.
* Develop and implement optimized layout designs for digital systems.
* Collaborate with cross-functional teams to ensure timely delivery of projects.
* Conduct thorough analysis and optimization of timing critical circuits.
* Stay up-to-date with emerging trends and technologies in the field of analog layout design.
Requirements:
* Minimum 5 years of experience in analog layout design.
* Experience with 65nm and below technologies (ideally 22nm and below).
* Strong understanding of timing critical circuits (PLLs, DLLs, clock distribution).
* Mastery of matching techniques for timing circuits and current cells.
* Chip finishing experience a plus.
* Familiarity with Cadence PVS/QRC/Pegasus tools.