Responsibilities
* Design and build SystemVerilog/UVM-based testbenches to validate computer vision IP structure, performance, and integration.
* Create advanced testing and automation frameworks to simulate real‑world conditions, continuous integration, and performance benchmarking.
* Work closely with Architecture, Software, Firmware, Design, Modelling, Emulation, and Post‑Silicon teams to define verification methodologies and test content.
* Develop and run diverse test content (directed, compliance, and system‑level scenarios), collect results, and analyse data for performance and issue tracking.
* Participate in micro‑architecture reviews and author clear technical documentation, feature descriptions, and verification reports.
Requirements
* Minimum 3 years in design verification using SystemVerilog/UVM and assertion‑based technologies; proven record in SoC or subsystem‑level verification.
* Proficiency in UVM, SystemVerilog, assertions, C++, and Python; strong understanding of testbench architecture, scripting, and automation workflows.
* Hands‑on experience with caches, DDR protocols, interconnects (APB, AHB, AXI, ACE, ACE‑Lite, NoC), and power/performance verification.
* Familiarity with emulation/prototyping platforms (Veloce, Palladium, Zebu, Protium, HAPS, QEMU), formal verification, and gate‑level/power‑aware simulations.
* Exposure to embedded firmware debugging, concurrency and stress testing frameworks, synthesizable transactors, and multiple successful tapeouts.
If this role is of interest please apply directly on LinkedIn or send a copy of your CV to alex@eu-recruit.com.
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