Job Overview:
We are seeking a highly skilled Verification Engineer to join our team. The ideal candidate will have a strong background in designing and developing complex IP Cores, specifically video encoder/decoder and computer vision hardware.
Key Responsibilities:
* Architect, design, implement, and testbench verification for computer vision IPs.
* Develop and maintain verification test benches and environments in System Verilog/UVM.
* Collaborate with cross-functional teams to define and develop test methodology and content.
* Participate in micro-architecture reviews, collect, organize, and execute system-level test content.
The successful candidate will work closely with team members to understand and align on feature development and meet targets. Strong technical documentation and feature description writing skills are essential.
Scripting and automation expertise (Python, Make, etc.) are required. Formal verification experience is a plus. A minimum of 2 years of DV experience using uvm/assertion based verification technologies is necessary.
About You:
Applicants must have a Bachelor's degree in Science, Engineering, or a related field. Experience in verifying complex SOC or SOC subsystems is essential. Familiarity with firmware/driver development using C++, successful tapeouts from conception to post silicon debug, and formal verification are highly desirable.
Skill proficiency in UVM, system verilog, assertion, C++, Python, Power Aware simulations, and caches and DDR memory protocol verification is required.