Design Verification Engineer for Mixed Signal IP
This role involves working on the verification of mixed-signal IP designs, including SerDes, DDR, and PLL. The ideal candidate will have experience in design and verification of hardware and software on SoCs and SoC/IP methodologies.
Key Responsibilities:
* Sv/Uvm based Design Verification of Serdes, Ddr & PlL
* Mixed-Signal PHY IP Emulation experience is desired along with Sv/UVM based simulation.
* Work closely with analog and digital front-end design teams to verify RTL and Analog/Mixed-Signal Designs in next-generation SerDes, DDR & PLL IP.
Required Skills and Qualifications:
* Bachelor's degree in Engineering, Computer Science or related field.
* Experience in design and verification of hardware and software on SoCs and SoC/IP methodologies.
* Knowledge in developing unit and SoC/IP level test benches using UVM.
Benefits:
* Salary and performance-related bonus.
* Maternity/paternity leave.
* Employee stock purchase scheme.
* Matching pension scheme.
* Education assistance.
* Relocation and immigration support (if needed).
As a Design Verification Engineer for Mixed Signal IP, you will be working in a collaborative environment with opportunities for growth and development. If you are passionate about designing and verifying complex hardware and software systems, we encourage you to apply for this exciting opportunity.