WHAT YOU DO AT AMD CHANGES EVERYTHING
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Together, we advance your career.
THE ROLE
The Memory Subsystem team at AMD is hiring a Senior Member of Technical Staff (SMTS) RTL and Integration Engineer to lead the definition, design, development, and integration of high-speed LPDDR/DDR memory subsystem solutions and associated IP.
This role includes technical ownership of key memory subsystem components across multiple product lines and close collaboration with architecture, verification, firmware, BIOS, and physical design teams across geographically distributed sites.
THE PERSON
You are a senior‑level RTL and integration engineer with deep technical expertise and a system‑level mindset. You are comfortable owning complex blocks or subsystems end to end, driving architecture discussions, and mentoring engineers through execution and debug.
Key Responsibilities
Own and drive RTL design and integration for memory subsystem IP and top‑level logic
Lead micro‑architecture definition and translate system requirements into robust RTL implementations
Integrate IP blocks to deliver complete DDR/LPDDR memory subsystems across product lines
Partner closely with verification teams on test strategy, debug, coverage, and pre‑silicon issue resolution
Collaborate with physical design teams on timing targets, floorplanning, CDC, and clocking strategies
Drive resolution of complex functional, timing, and integration issues across subsystem boundaries
Develop and maintain high‑quality subsystem documentation, interface definitions, and timing diagrams
Support pre‑silicon and post‑silicon bring‑up and work with firmware and BIOS teams to enable features
Mentor and technically guide other engineers, promoting best practices and design quality
Required Qualifications
Expert proficiency in Verilog and SystemVerilog for RTL design
Extensive experience designing and integrating IP and subsystems in complex SoC environments
Strong understanding of memory subsystem architecture and micro‑architecture
Expert knowledge of clocking, resets, CDC, and synchronization techniques
Proven ability to debug complex RTL and integration issues using simulation and emulation tools
Experience leading technical efforts and collaborating across design, verification, firmware, and physical design teams
Strong experience using Git and/or Perforce
Preferred Experience
Hands‑on experience with DDR/JEDEC standard IP, DDR PHY, memory controllers, or full memory subsystems
Experience serving as technical owner for subsystem or major IP blocks
Knowledge of SVA/OVL and synthesizable assertions
Experience with VCS and Zebu emulation for debug and bring‑up
Strong understanding of power management, UPF, and low‑power design techniques
Experience analyzing system‑level performance, power, and architectural tradeoffs
ACADEMIC CREDENTIALS
Bachelor’s or Master’s degree (or equivalent) in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
LOCATION
Ireland (Dublin or other AMD Ireland locations; hybrid working supported).
Employment is contingent on meeting applicable export control and security requirements.
#Ireland
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
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