Job Title: UVM Design Verification EngineerWorking with a globally leading Semiconductor company on cutting-edge ASICs, SoCs, and IPs.Responsibilities:Perform verification planningDevelop verification environment from scratch using UVMConduct functional verification and achieve code coverageDefine and implement test casesSupport regression debugging and develop flow/infrastructureVerify ASICs, ICs, and SoCsSkills:Knowledge of SystemC / C / C++ is a plusProficiency in scripting languages such as Python, CSH, Make#verification #UVMBy applying, you acknowledge that we may collect and process your personal data as described in our Privacy Notice.Seniority levelMid-Senior levelEmployment typeFull-timeJob functionEngineering, Design, and ResearchIndustriesSemiconductor ManufacturingComputer Hardware ManufacturingElectronics Manufacturing
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