We are looking for candidate who can code Pegasus DRC/LVS runsets based on given design rules document or given spec from customers or foundry partners.
Develop automation to run regressions, auto detect issues and generate validation reportsYou are also expected to file bug reports and work closely with R&D team.Support customers on tool bugs, developments/improvements to enhance performance, add functionality and improve capacityQualificationsBS degree with 1+ years of experience or MS degree in electrical engineering, computer science or equivalent.Experience and Technical Skills requiredExperience in Developing Calibre/ICV/Assura/Pegasus runsets (DRC, LVS, Antenna) and validating testcases.Experience in DRC/LVS debugging for advanced nodes.Familiar with Chip fabrication process and 3DIC chip integration.Fluent in at least one of the following : TCL, Python, Unix-Linux platformsBehavioral skills requiredMust possess strong written, verbal and presentation skillsAbility to establish a close working relationship with peers and managementExplore what's possible to get the job done, including creative use of unconventional solutionsWork effectively across functions and geographiesPush to raise the bar while always operating with integrityCadence is committed to equal employment opportunity and employment equity throughout all levels of the organization.
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