Job Title: High-Speed Verification Engineer
* In this critical role, you will lead the development and execution of verification plans for cutting-edge mixed-signal PHY IPs.
The team is at the forefront of silicon node technology, working with leading-edge tools and verification techniques in 3nm and below nodes.
Key Responsibilities include:
• Collaborating closely with analog and digital design teams to drive innovation
• Interacting with architecture physical design software test teams to integrate Ser Des DDR PLL IP designs into next-generation Snapdragon products ----------------------------------- The ideal candidate will have a strong background in SV/UVM based Design Verification techniques. Strong knowledge of mixed-signal circuit design principles is also required. Additionally, proficiency in current industry-standard EDA tools such as VCS/Vivado/Mentor Graphic Tools would be beneficial.