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Client:
CADENCE IRELAND
Location:
Cork, Ireland
Job Category:
Other
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EU work permit required:
Yes
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Job Reference:
12ae81fcefd3
Job Views:
3
Posted:
01.06.2025
Expiry Date:
16.07.2025
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Job Description:
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware, and IP that turn design concepts into reality.
Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial, and health.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Job Title: Senior Principal Analog Design Engineer (SERDES)
Location: Cork/Dublin
Reports to: Group Director
Job Overview:
The Cadence Serdes PHY team based at our R&D center of excellence in Cork is seeking ambitious analog designers who wish to work on the leading edge of Wireline technology at the highest data rates (112Gbps+) and on the smallest technology nodes (e.g., 3nm).
The PHY team designs products for communication protocols such as PCIe (now at Gen 7) and UCIe (emerging Chiplets standard).
The Senior Principal Analog Design Engineer will take a technical leadership role on the PMA design team as part of a SERDES product team.
Job Responsibilities:
* Design of high-speed SERDES products at data rates up to and exceeding 112 Gbps on leading-edge technology nodes (e.g., 3nm FinFET CMOS)
* Design and development of analog/mixed-signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications
* Work closely with physical design engineers to design IC circuit blocks and PMA sections
* Participate in technical leadership of the team in the areas of circuit design and SERDES architectures
* Collaborate with global teams across different time zones (US, west coast, east coast)
Job Qualifications:
* Minimum of 7 years of experience in CMOS SERDES or high-speed I/O IC design and development
* Knowledge of common SERDES standards and electrical requirements
* Thorough understanding of jitter and signal equalization techniques
* Proficient in designing various SERDES circuit blocks: Driver, Receiver, Serializer, Deserializer, Phase Interpolator, Low jitter PLL, High-Speed Clock Distribution, Bias and Bandgap, Voltage Regulators
* Excellent problem-solving skills, analog aptitude, good communication skills, and team collaboration ability
* BEng, MEng, or PhD degree
Additional Skills/Preferences:
* Experience with Cadence tools and design experience at >10Gbps
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