Work as a Verification Specialist to drive the success of our projects by developing and implementing verification strategies. Collaborate with cross-functional teams to understand design features and create effective verification plans.
Key Responsibilities
* Develop test plans and documents for design features, ensuring alignment with design team goals.
* Create verification components and testbenches for low power verification, integrating third-party VIPs/UVCs as needed.
* Establish constraint random verification environments using System Verilog and UVM.
* Foster a culture of innovation by working with tool vendors to improve verification flows.
Requirements
* Bachelor's degree in Science, Engineering, or a closely related field.
* 1+ years of hands-on experience in System Verilog, OVM/UVM based constrained random verification.
* 1+ years of experience in developing verification components/UVCs, testbench for RTL verification.
What We Offer
* A dynamic work environment that encourages collaboration and creativity.
* Opportunities for growth and professional development.
* A competitive salary and benefits package.
* Relocation support for international candidates.