We are excited to be partnered with a leading technology company at the forefront of driving digital transformation for a connected future. They are seeking several ASIC Design Verification Engineers to join their team and contribute to a wide variety of engineering projectsResponsibilities:Deploying Industry-Leading Verification Methodologies such as UVM and Formal VerificationDeveloping Testbenches and Verification Components such as UVCs, C models, and Vertical/Horizontal re-usable Verification Environments.Verifying sensor algorithms RTL for ASIC tapeout quality deliveryTest plan development based on Design documents and interaction with design/systems engineersImplementing C model integration within UVM framework.Requirements:3+ years ASIC design verification, UVM-based functional verification, or related work experienceExperienced with constrained-random verification environment and flow build-up with UVM, Coverage-Driven verification methodologyExperience in SystemC, Matlab and formal verification tools (Jasper or VC_Formal etc) would be considered an advantageFamiliarity with C/C++By applying to this role you understand that we may collect your personal data, store and process it on our systems. For more information please see our Privacy Notice (https://eu-)