Job Description:
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* The SerDes PHY team designs products for communication protocols such as PCIe (now at Gen 7) and UCIe (emerging Chiplets standard).
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* Participate in the architecture & implementation of high-speed communication protocols.
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* Work with cross-functional teams ranging from architecture, circuit design, Layout development, RTL design & Validation, Physical design & Test chip development.
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Requirements:
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* BEng, MEng or PhD degree.
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* Candidate's background should include a minimum of 3 years of experience in CMOS SERDES or high-speed I/O IC design and development.
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* Working knowledge of a set of common SERDES standards is desirable.
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* Prior experience in RTL design & synthesis is expected.
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* Excellent problem-solving skills and ability to work cooperatively in a team environment.
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* Excellent communication and stakeholder management skills.
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Key Responsibilities:
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* Design of High Speed SERDES products at data rates up to and exceeding 112 Gbps on leading edge technology nodes.
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* Work with global teams which work in different time-zones.
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