Company:QT Technologies Ireland LimitedJob Area:Engineering Group, Engineering Group > ASICS EngineeringGeneral Summary:As a member of the Graphics team, you will help develop new flows, methodologies, and algorithms to improve power, performance, and area (PPA) on state‑of‑the‑art GPU cores while working closely with the graphics microarchitecture design and implementation teams. You will possess a basic understanding of RTL design and the ASIC design flow from RTL to GDS, including synthesis, static timing analysis, formal verification, physical design, ECO generation, and verification. You will collaborate with multiple functional teams—including design, technology, power, implementation, sign‑off, and post‑silicon—to drive PPA improvements into GPU cores.Knowledge and Experience:Implementation and delivery of GPU cores from RTL to GDSIISemi‑custom design flow and methodology developmentIdentifying areas for flow and process improvementsVerilog and System‑Verilog languagesRTL synthesis using physically aware toolsDesign constraint management for power, timing, clocking, interfacesFormal verification for RTL‑netlist and netlist‑netlist checksClock tree analysis and optimizationECO methods for functional and timing fixesManaging design goals and tradeoffs in power, performance, and areaPreferred Qualifications:At least 5–7 years of experience developing methodologies for PPA improvementBasic understanding of digital design and RTL developmentHands‑on experience with EDA tools such as Synopsys Fusion Compiler, Synopsys RTL‑Architect, PrimePower, PrimeTime, and Prime ClosureScript writing experience in Unix shell, Python, Perl, and/or TCLExcellent interpersonal and analytical skills and ability to work independentlyHighly motivated, excellent team spirit, obsession with deliverable quality and customer orientationPreferred education: Master’s in Computer Engineering, Computer Science, or Electrical EngineeringRequired education: Bachelor’s in Computer Engineering, Computer Science, or Electrical EngineeringMinimum Qualifications:Bachelor’s degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experienceMaster’s degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experiencePhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experienceBenefits:Salary, stock, and performance-related bonusMaternity/Paternity leaveEmployee stock purchase schemeMatching pension schemeEducation assistanceRelocation and immigration support (if needed)Life, medical, income, and travel insuranceSubsidised memberships for physical and mental well‑beingBicycle purchase schemeEmployee run clubs (running, football, chess, badminton, and many more)Equal OpportunityWe are an Equal Opportunity employer; all qualified applicants will receive consideration for employment without regard to race, colour, religion, sexual orientation, gender identity, national origin, disability, veteran status, or any other protected classification.
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