Social network you want to login/join with: Digital Verification Engineer Working experience with I2 C, SPI, and other protocols Good understanding of ASIC design flow Familiarity with System Verilog and UVM implementation Experience in setting up UVM test benches from scratch and developing UVM components Experience in establishing GLS verification environments Hands-on experience with Assertions and Functional Coverage Automation of verification flow using Python/Perl in an industrial setting Independent, self-motivated, team player, and able to follow through Understanding of analog behavioral models (added advantage)Automotive experience and requirements management experience are highly desirable
#J-18808-Ljbffr