**High-Speed Analog Design Engineer Position**
We are seeking a highly skilled and ambitious analog designer to join our team in the development of cutting-edge SerDes products. The successful candidate will be responsible for designing high-speed IC circuit blocks from initial concept through final verification, working closely with Physical Design Engineers to design PMA sections.
The ideal candidate will have a minimum of 3-5 years of experience in CMOS SERDES or high-speed I/O IC design and development, with a strong understanding of jitter and signal equalization techniques. Proficiency in designing various SERDES circuit blocks, such as drivers, receivers, serializers, deserializers, phase interpolators, low jitter PLLs, high-speed clock distribution, bias, and bandgap circuits is essential.
We value candidates with excellent problem-solving skills, analog aptitude, good communication skills, and the ability to work cooperatively in a team environment. Education: BEng, MEng, or PhD in Electrical Engineering or a related field is required.
Additionally, experience with Cadence tools and design experience at >10Gbps is advantageous. If you are interested in publishing academic papers and presenting at conferences, such as ISSCC or JSSC, we encourage you to apply.
Key Responsibilities:
* Design high-speed IC circuit blocks from initial concept through final verification
* Work closely with Physical Design Engineers to design PMA sections
* Develop expertise in various SERDES circuit blocks
* Collaborate with global teams to achieve project goals
Requirements:
* BEng, MEng, or PhD in Electrical Engineering or a related field
* Minimum 3-5 years of experience in CMOS SERDES or high-speed I/O IC design and development
* Strong understanding of jitter and signal equalization techniques
* Proficiency in designing various SERDES circuit blocks