High Level Synthesis Engineer
European Tech Recruit are working closely with a leading semicon company, based in the county Cork area, who are looking for a talented
HLS Engineer
to join their team
.
Responsibilities as
HLS Engineer:
Taking high-level algorithms and translating them into efficient RTL using HLS tools.
Breaking down complex algorithms into hardware-achievable components.
Optimizing designs for performance, area, and power constraints.
Guiding HLS tools with directives and constraints to achieve desired outcomes.
Collaborating with RTL designers to ensure smooth integration of HLS-generated modules.
Developing and executing verification test benches for HLS-generated designs.
Performing hardware bring-up and debugging.
Requirements:
2+ years of experience in digital design, RTL design (Verilog/SystemVerilog), or FPGA design.
Extensive experience with high-level programming languages like C/C++.
Experience with HLS tools for ASIC or FPGA design.
(Stratus, Catapult or Vivaldo).
Knowledge of basic processor architecture.
Understanding of HLS concepts such as scheduling, resource allocation, and optimization techniques like pipelining and Algorithm partitioning.
Familiarity with the full ASIC design cycle, from specification to bring-up, is often preferred.
Experience with hardware verification, simulation, and timing closure.
If this role is of any interest please apply directly on LinkedIn or send a copy of your CV to -
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