A Global semiconductor giant based in Cork are seeking to bolster their team with a talented EVA/Video Design Verification Engineer.
Please note this opportunity is based on-site in Cork.
Responsibilities
Architect and develop advanced SystemVerilog/UVM-based testbenches to verify the structure, functionality, and performance of computer vision IPs.
Design and maintain scalable verification environments, leveraging automation and continuous integration frameworks for efficient regression and testing.
Collaborate cross-functionally with Architecture, Software, Firmware, Design, Modeling, and Validation teams to define verification strategies, methodologies, and content.
Execute and analyze diverse verification content, including directed tests, compliance suites, and system-level scenarios, applying data-driven analysis to identify and resolve issues.
Document and review verification plans, micro-architecture designs, and feature descriptions to ensure clarity and alignment across development teams.
Requirements
3+ years of experience in design verification using SystemVerilog, UVM, and assertion-based methodologies for complex SoCs or subsystems.
Proficiency in scripting and automation, with hands-on skills in Python, Make, and CI frameworks; experience in benchmarking, performance, and power verification.
Strong understanding of interconnect and memory protocols (APB, AHB, AXI, ACE, DDR), cache systems, and VIP-based memory verification flows.
Experience with advanced verification tools, including formal verification, emulation/prototyping (Veloce, Palladium, Zebu, Protium, etc.), and gate-level simulations.
Technical expertise in UVM, SystemVerilog, C++, and power-aware simulations; familiarity with emulation transactors, monitors, and scoreboards is a plus.
If this role is of interest please apply directly on LinkedIn or send a copy of your CV to -
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