OverviewOur client, a leading Multinational Semiconductor EDA Software provider, has an opening for Principal Digital Design Verification Engineer (SerDes) for role based in Cork City, Ireland.RoleAs Principal Verification Engineer (SerDes) you will take a Technical Leadership role on the Verification team (Digital & AMS) as part of a SERDES Product Team located at Cork, Ireland.You will be working on the leading edge of Wireline technology at the highest data rates (112Gbps+) and on the smallest technology nodes (e.g. 3nm).The PHY team designs products for communication protocols such as PCIe (now at Gen 7) and UCIe (emerging Chiplets standard).ResponsibilitiesVerification of High Speed SERDES products at data rates up to and exceeding 112 Gbps on leading edge technology nodes (e.g. 3nm FinFET CMOS)Specification, Design and Verification of High Speed PHY IP based on communication protocols (PCIe, Ethernet)Verification from initial concept/specification through final verification of conformance to customer specifications using Coverage metric Implementation, Tracking and ClosurePrototyping, Emulation, Customer delivery and supportWork with cross-functional teams ranging from architecture, all aspects of circuit design, Layout development, RTL design & Validation, Physical design & Test chip developmentParticipate in technical leadership of the team in the areas of digital design and verification, SERDES architecturesWork with global teams (US, west coast and east coast), which work in different time-zonesEducationBEng, MEng, PhD or equivalentExperienceCandidate’s background should include a minimum of 7 years of experience in CMOS SERDES or high-speed I/O IC design and developmentWorking knowledge of a set of common SERDES standardsWide experience with digital design and verification tools; RTL design using Verilog & verification with System Verilog and UVMExperience of Assertion Based Formal Verification essentialExperience of Front-end design tools covering LINT, Synthesis & CDC AnalysisExcellent problem-solving skills and ability to work cooperatively in a team environmentExcellent communication and stakeholder management skillsAdvantageous SkillsPrior experience with post Silicon validation & customer IP deployment of one or more Serial IO IPs/ complex Memory Interface IPs is an added advantageKnowledge of PCIe, CXL protocols preferredContactFor further information please contact Mícheál at Software Placements on 00353 1 5254642 or email micheal@softwareplacements.ie
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