A Global semiconductor giant based in Cork are seeking to bolster their team with a talented HLS engineer.Responsibilities:Translate high-level algorithms into efficient RTL using HLS tools for ASIC or FPGA designs.Decompose complex algorithms into hardware-implementable components.Optimise designs for performance, area, and power efficiency.Apply HLS tool directives and constraints to guide synthesis outcomes.Collaborate with RTL designers to ensure seamless integration and perform verification, testing, and hardware bring-up.Requirements:Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.2+ years of experience in digital design, RTL (Verilog/SystemVerilog), or FPGA development.Proficiency in high-level programming languages such as C/C++, with scripting experience in Python or TCL as a plus.Experience with HLS tools for ASIC or FPGA (e.g., Stratus, Catapult, Vivaldo) and understanding of HLS concepts like scheduling, resource allocation, pipelining, and algorithm partitioning.Familiarity with the full ASIC design cycle, hardware verification, simulation, timing closure, and hardware debugging.If this role is of interest please apply directly on LinkedIn or send a copy of your CV to -By applying to this role you understand that we may collect your personal data and store and process it on our systems. For more information please see our Privacy Notice (https://eu-)