Lead Digital Design Engineer
As a senior member of the digital design group, you will be responsible for taking ownership of complex IP blocks and driving architectural, implementation, and verification decisions.
Within a high-performing engineering team, you will collaborate cross-functionally with systems, analog, verification, and physical design teams to deliver high-quality silicon solutions to market.
Key responsibilities include leading the design and development of digital IP for ASIC or FPGA platforms, defining architecture and contributing to specification development, delivering high-quality RTL using Verilog or VHDL, guiding and reviewing synthesis, timing closure, and integration activities, and working with verification teams on functional coverage and UVM-based testbenches.
Additionally, you will mentor junior engineers and provide technical leadership across projects. A strong background in RTL design is required, as well as experience with industry-standard EDA tools for synthesis, timing, and simulation.
Requirements:
* 7+ years of experience in digital design within a semiconductor or related environment
* Strong RTL design expertise (Verilog/VHDL), with a solid understanding of SoC architecture
* Proven experience with industry-standard EDA tools for synthesis, timing, and simulation
* Exposure to SystemVerilog and UVM-based verification environments
* Experience with low-power design techniques, clock domain crossing, and DFT is advantageous
* Degree in Electronic Engineering, Computer Engineering, or related field
Join us in this exciting opportunity to drive innovation and excellence in digital design.