Are you a seasoned leader passionate about optimizing Power, Performance, and Area (PPA) in microprocessor design?
* This role offers an exceptional opportunity to lead and manage a high-performing team of engineers dedicated to Microprocessor Physical Design implementation and signoff.
* Applicants should have extensive knowledge and hands-on experience in Physical Design, Timing Closure, and Signoff to deliver high-quality results.
* The ideal candidate will be able to mentor and coach engineers to enhance their skills and promote positive team culture.
* A key responsibility is to collaborate closely with RTL teams to continuously improve PPA metrics.
* Driving flow development and automation scripting is also essential for this position.
Main Responsibilities:
1. Lead a team of engineers
2. Apply knowledge of Physical Design
3. Mentor engineers
4. Collaborate with RTL teams
5. Drive flow development
Requirements:
* 15+ years of experience in SoC Physical Design implementation, signoff, and TapeOut
* Proven leadership experience managing Physical Design teams
* Exceptional analytical and problem-solving skills
* Strong communication and time management skills
* Proficiency with industry-standard EDA tools
About Us:
We push the limits of innovation to solve the world's most important challenges.
Our Mission:
* Build great products that accelerate next-generation computing experiences
* Accelerate the building blocks for data centers, artificial intelligence, PCs, gaming, and embedded solutions