A Global semiconductor giant based in Cork are seeking to bolster their team with a talented Power Integrity Design Engineer.Please note this opportunity is based on-site in Cork and requires rights to work in Ireland already in place before starting.ResponsibilitiesPerform PDN checks (IR-drop, ESD, EM) for complex cores and full-chip SoCs.Develop new techniques, methodologies, and flows for PDN analysis, optimization, and sign-off.Collaborate with design, Physical Design, and STA teams on use-case selection, power analysis, and Vmin assessment.Ensure compliance with power-integrity signoff criteria and proactively resolve PDN issues throughout development.Build automation solutions for PDN and power data mining, processing, and reporting.RequirementsExpertise with PDN/EMIR tools such as RedHawk, RHSC, Voltus, and PTPX for flat and hierarchical SoC analyses.Strong understanding of ASIC design flows (RTL-to-GDS) including synthesis, floorplanning, PnR, CTS, STA, and timing closure.High proficiency in automation and scripting (Python, TCL, or Perl).Experience with package design, system-level PDN or thermal analysis, circuit simulation, or multi-die (2.5D/3D) packaging is a plus.Excellent problem-solving, communication, and collaboration skills, with 3+ years of relevant industry experience.If this role is of interest please apply directly on LinkedIn or send a copy of your CV to -By applying to this role you understand that we may collect your personal data and store and process it on our systems. For more information please see our Privacy Notice (https://eu-)