Principal Analog Layout Engineer, Galway
Client: Chipright
Location: Galway, Ireland
EU work permit required: Yes
Job Description:
Principal Analog Layout Engineer
Minimum 5 years experience but ideally >8+ years Experience
Experience in 65nm and below (ideally 22nm and below)
Understanding of layout for critical timing (PLL, DLL, clock distribution)
Understanding of matching techniques for timing circuits and current cells
Chip finishing experience a bonus
Experience with Cadence PVS/QRC/Pegasus
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