**Analog Layout Design Engineer Role**
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This is an exciting opportunity to work as a skilled Analog Layout Design Engineer. As part of our team, you will be responsible for designing layouts for digital and analog circuits based on schematics using industry-leading CAD tools and cutting-edge foundry technology.
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Main Responsibilities:
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* Designing layouts for basic digital and analog building blocks using analog transistor level components
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* Laying out analog macros, power pads, and input/output pads using above blocks
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* Working closely with Analog designers in floorplanning; power grid and signal flow planning
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* Physical and electrical verification including DRC, LVS, EM/IR, ERC, PERC Latch up and PERC ESD
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* Creative blackbox models for other groups in the design flow
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Requirements:
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We are looking for experienced professionals with detailed knowledge of CMOS circuit theory, excellent communication skills, and proficiency in layout design and verification using Cadence Virtuoso and Mentor Calibre tools.
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A minimum of 5 years of relevant or comparable experience doing analog layout design is required. Knowledge of chip level integration and ESD concepts is a plus.
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You should be able to work well as part of a team and have a good understanding of signal and clock shielding and isolation techniques.
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Qualifications:
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* Bachelor's degree in Engineering (or related field)
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* Associates Degree in Engineering
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Benefits:
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We offer a range of benefits, including competitive salary, comprehensive health insurance, and opportunities for professional growth and development.
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Please note that we are an equal opportunity employer and welcome applications from all qualified candidates.
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We encourage applicants to apply through our careers page.
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Key Skills and Qualifications:
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* Detailed knowledge of CMOS circuit theory
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* Excellent communication skills
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* Proficiency in layout design and verification using Cadence Virtuoso and Mentor Calibre tools
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* Minimum 5 years of relevant or comparable experience doing analog layout design
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* Knowledge of chip level integration and ESD concepts
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* Ability to work well as part of a team
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* Good understanding of signal and clock shielding and isolation techniques
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