A Global semiconductor giant based in Cork is seeking to bolster their team with a talented design verification engineer.
Key Responsibilities
Develop and implement SystemVerilog/UVM testbenches for complex video and computer vision IP blocks.
Create and validate power-aware testbenches using UPF to ensure low-power design verification.
Execute functional, power-aware, gate-level, and formal verification simulations.
Debug and resolve issues across simulation and post-silicon environments.
Collaborate with RTL, DFT, PD, and firmware teams and mentor junior engineers.
Requirements
Bachelor's or Master's degree in Computer/Electrical Engineering, Computer Science, or related field.
5+ years of experience in design verification, preferably with video or computer vision IP.
Strong expertise in SystemVerilog, UVM, and power-aware verification methodologies (UPF).
Proficiency in scripting languages such as Python or Perl and firmware interaction using C++/Python.
Demonstrated ability to work cross-functionally and lead technical challenges in large organisations.
If this role is of interest please apply directly on LinkedIn or send a copy of your CV to
By applying to this role you understand that we may collect your personal data and store and process it on our systems.
For more information please see our Privacy Notice
#J-*****-Ljbffr