Job Description
Our team is currently seeking talented analog/mixed-signal designer engineers to work on DLL/PLL, Rx/Tx IO blocks and next-generation high frequency related circuits.
As a key member of our Analog Mixed-Signal IP (MSIP) team, you will be directly involved in delivering next-generation analog/mixed-signal block designs for our DDR and Chip-to-Chip PHY team.
The ideal candidate will have experience in architecture, design and development of mixed-signal circuits for LPDDR5/6 and next-generation Chip-to-Chip PHY systems.
You will be working closely with the Analog Mask Layout and Physical Design teams to deliver IP on the latest technology nodes.
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Key Responsibilities:
* Architecture, design and development of mixed-signal circuits for LPDDR5/6 and next-generation Chip-to-Chip PHY systems.
* Custom blocks include high-speed Rx/Tx, clock distribution, clocking delay elements (DLL/PLL), references blocks and band-gap circuits.
* Custom schematic capture, SPICE analysis and exhaustive pre-silicon validation.
* Post-silicon bringup support and system enablement.
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Requirements:
1. Master's or Ph.D. degree in Science, Engineering, or related field.
2. 5+ years of transistor level analog mixed-signal design experience, preferably in high-speed wireline SerDes, PLL, DDR or other high speed applications.
3. Experience in SPICE simulators and schematic capture tools.
4. Experience in designing op-amps, bandgaps, differential amplifiers, VCO, PLL, DLL.
5. Understanding of signal integrity in high-speed wireline design is preferred.
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What We Offer
* Salary and performance-related bonus.
* Stock options.
* Maternity/Paternity Leave.
* Employee stock purchase scheme.
* Matching pension scheme.
* Education Assistance.
* Relocation and immigration support (if needed).
* Life, Medical, Income and Travel Insurance.