Senior Design Engineer for Analog and Mixed Signal Circuits
This key role involves designing critical circuit blocks and collaborating closely with layout engineers to ensure layouts are fully optimized.
* Analyze architecture analysis IP delivery Fin FET GAA process technology nodes at 3nm below.
* Create behavioral models, set up, run, analyze circuit simulations, perform quality assurance procedures developed hard macros deliver hard macros support customer integration testing silicon characterization analysis prepare verification reports
About the Position:We are part of a large team involved in next-generation Ser Des PLL designs SoCs leading-edge Fin FET GAA technologies.
The successful candidate will be required onsite days per week