Senior IP Verification Engineer
You will take full responsibility for verification of a design, whether it is a block or sub-system.
Responsibilities include:
1. Define and implement UVM-based test environments.
2. Break down requirements and create verification specifications, including verification strategy for the design object and associated verification plan.
3. Execute verification strategy by creating UVM test benches.
4. Develop, run, and debug test cases.
5. Work with coverage closure to meet quality goals.
6. Continuously improve and optimize working methods.
7. Generate documentation.
8. Develop competence in the technical domain.
To be successful in this role, you must have:
1. An MSc degree in a technical field or equivalent education.
2. 8+ years of experience in verification using SystemVerilog and UVM.
3. Experience in developing verification test plans and directed/randomized test cases.
4. Good team cooperation skills.
5. Good communication skills in English.
6. Results-driven with the ability to meet expectations.
Additional requirements include:
1. Experience using Cadence verification suite.
2. Experience using vManager and vPlans.
3. Experience from Formal Verification.
4. Experience working in an Agile environment.
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